Introduction to Systemverilog | 誠品線上

Introduction to Systemverilog

作者 Ashok B. Mehta
出版社 Ingram International Inc
商品描述 Introduction to Systemverilog:,:誠品以「人文、藝術、創意、生活」為核心價值,由推廣閱讀出發,並透過線上網路,傳遞博雅的溫度,打造全新的文化場域。

作者介紹

作者介紹 Ashok Mehta is an ASIC CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on "SystemVerilog Assertions and Functional Coverage" and second on "ASIC Functional Design Verification - A guide to technologies and methodologies". His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.

商品規格

書名 / Introduction to Systemverilog
作者 / Ashok B. Mehta
簡介 / Introduction to Systemverilog:,:誠品以「人文、藝術、創意、生活」為核心價值,由推廣閱讀出發,並透過線上網路,傳遞博雅的溫度,打造全新的文化場域。
出版社 / Ingram International Inc
ISBN13 / 9783030713218
ISBN10 /
EAN / 9783030713218
誠品26碼 /
語言 / 3:英文
級別 / N:無
頁數 / 852
重量(g) / 0.0
尺寸 / 0.0X0.0X0.0CM
重量(g) / 1451.5
裝訂 / P:平裝
尺寸 / 22.8X13.8X3.6CM