System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications | 誠品線上

System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

內容簡介

內容簡介 This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC SoC CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions Operators explanations are enhanced, with the addition of more examples and figures. - Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; - Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; - Provides pract[未完, 尚有資料...]

作者介紹

作者介紹 Ashok Mehta has been working in the ASIC SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium design team) and after a route of a couple of startups, worked at Applied Micro and TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs and at TSMC he released two industry standard Reference Flows that establish Reuse of Verification Environment from ESL to RTL. Lately, he has been researching 3DIC design verification challenges at TSMC which is where SystemVerilog Assertions played an instrumental role in stacked die SoC design verification. Ashok earned an MSEE from University of Missouri. He holds 18 U.S. Patents in the field of SoC and 3DIC design verification.

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